4 search results - page 1 / 1 » Optimal Termination of On-Chip Transmission-Lines for High-S... |
IEICET
2007
13 years 4 months ago
2007
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...
ICCD
1994
IEEE
13 years 8 months ago
1994
IEEE
This paper presents a simple and robust method of designing the lossy-transmission-line interconnects in a network for multichip modules. This method uses wire-sizing entirely to ...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of curre...