106 search results - page 1 / 22 » Optimal Vector Selection for Low Power BIST |
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
ET
2000
13 years 4 months ago
2000
DSD
2005
IEEE
13 years 10 months ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
SAC
2008
ACM
13 years 4 months ago
2008
ACM
We systematically evaluate a recently proposed method for unsupervised discrimination power analysis for feature selection and optimization in multimedia applications. A series of...
GLVLSI
2007
IEEE
13 years 6 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...