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» Optimal Wire-Sizing Function with Fringing Capacitance Consi...
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ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
13 years 8 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
ICCAD
1997
IEEE
118views Hardware» more  ICCAD 1997»
13 years 9 months ago
Global interconnect sizing and spacing with consideration of coupling capacitance
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of couplin...
Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang P...
ASPDAC
1998
ACM
79views Hardware» more  ASPDAC 1998»
13 years 9 months ago
Simultaneous Wire Sizing and Wire Spacing in Post-Layout Performance Optimization
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
Jiang-An He, Hideaki Kobayashi
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Wire sizing with scattering effect for nanoscale interconnection
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...
Sean X. Shi, David Z. Pan