8 search results - page 2 / 2 » Optimal equivalent circuits for interconnect delay calculati... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
ISLPED
2007
ACM
13 years 6 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...