19 search results - page 2 / 4 » Optimal non-uniform wire-sizing under the Elmore delay model |
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
— In this paper, we present a new interconnect delay model called Fitted Elmore delay (FED). FED is generated by approximating Hspice delay data using a curve fitting technique....
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...