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» Optimal non-uniform wire-sizing under the Elmore delay model
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DATE
2002
IEEE
74views Hardware» more  DATE 2002»
13 years 10 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
ICCAD
1997
IEEE
89views Hardware» more  ICCAD 1997»
13 years 8 months ago
Optimal shape function for a bi-directional wire under Elmore delay model
In this paper, we determine the optimal shape function for a bi-directional wire under the Elmore delay model. Given a bi-directional wire of length L, let fx be the width of the ...
Youxin Gao, D. F. Wong
ICCAD
1996
IEEE
74views Hardware» more  ICCAD 1996»
13 years 9 months ago
Optimal non-uniform wire-sizing under the Elmore delay model
We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: 1) total weighted sink-delays; 2) total area...
Chung-Ping Chen, Hai Zhou, D. F. Wong
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
13 years 9 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 10 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...