64 search results - page 2 / 13 » Optimal register assignment to loops for embedded code gener... |
ICS
2009
Tsinghua U.
14 years 2 days ago
2009
Tsinghua U.
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
IEEEPACT
2002
IEEE
13 years 10 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
CC
2003
Springer
13 years 10 months ago
2003
Springer
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...