Array Index Allocation under Register Constraints in DSP Programs

Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algorithms show special characteristics usually not found in general-purpose computing. Since real-time constraints imposed on DSP algorithms demand for very high quality machine code, high-level language compilers for DSPs should take these characteristics into account. One important characteristic of DSP algorithms is the iterative pattern of references to array elements within loops. DSPs support e cient address computations for such array accesses by means of dedicated address generation units AGUs. In this paper, we present a heuristic code optimization technique which, given an AGU with a xed number of address registers, minimizes the number of instructions needed for address computations in loops.1

• Type: Conference
• Year: 1999
• Where: VLSID
• Authors: Anupam Basu, Rainer Leupers, Peter Marwedel
• Keywords: DSP Algorithms, DSPs, Signal Processors Dsps, VLSI, VLSID 1999