54 search results - page 2 / 11 » Optimal simultaneous mapping and clustering for FPGA delay o... |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...