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FPGA
2008
ACM

Mapping for better than worst-case delays in LUT-based FPGA designs

8 years 5 months ago
Mapping for better than worst-case delays in LUT-based FPGA designs
Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experienced, forcing designers to reduce performance requirements in order to reserve larger margins. Better than worst-case design can be used to address the variability problem, as well as breaking the performance limit set by the worst-case delay in the conventional design style, even without the consideration of delay variation. In this paper we will present a novel methodology for measuring and optimizing the performance of circuits to operate with the clock period smaller than the worst-case delay. We also develop a novel technology mapping algorithm that optimizes circuits under such a metric. Using our novel mapping algorithm named BTWMap (Better Than Worst-case Mapper) and its area-optimized version named BTWMap+area, we are able to improve the overall circuit latency by 13% and 11%, respectively. Categories a...
Kirill Minkovich, Jason Cong
Added 26 Oct 2010
Updated 26 Oct 2010
Type Conference
Year 2008
Where FPGA
Authors Kirill Minkovich, Jason Cong
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