44 search results - page 2 / 9 » Optimality study of logic synthesis for LUT-based FPGAs |
DAC
2000
ACM
14 years 6 months ago
2000
ACM
In this paper, we study the incremental t echnology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-lev...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
TCAD
2011
12 years 11 months ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
ERSA
2004
13 years 6 months ago
2004
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
FPGA
2007
ACM
13 years 11 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...