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VLDB
2005
ACM
113views Database» more  VLDB 2005»
11 years 6 months ago
Optimistic Intra-Transaction Parallelism on Chip Multiprocessors
With the advent of chip multiprocessors, exploiting intra-transaction parallelism is an attractive way of improving transaction performance. However, exploiting intra-transaction ...
Christopher B. Colohan, Anastassia Ailamaki, J. Gr...
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
10 years 5 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
ISCA
2003
IEEE
183views Hardware» more  ISCA 2003»
11 years 6 months ago
The Jrpm System for Dynamically Parallelizing Java Programs
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with...
Michael K. Chen, Kunle Olukotun
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
11 years 5 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
11 years 6 months ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta
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