6 search results - page 1 / 2 » Optimization of Test Accesses with a Combined BIST and Exter... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
BMCBI
2008
13 years 4 months ago
2008
Background: Protein structure prediction and computational protein design require efficient yet sufficiently accurate descriptions of aqueous solvent. We continue to evaluate the ...
ICALP
2009
Springer
14 years 4 months ago
2009
Springer
We initiate the study of sublinear-time algorithms in the external memory model [14]. In this model, the data is stored in blocks of a certain size B, and the algorithm is charged...
PROPERTYTESTING
2010
13 years 2 months ago
2010
We initiate the study of sublinear-time algorithms in the external memory model [Vit01]. In this model, the data is stored in blocks of a certain size B, and the algorithm is char...