66 search results - page 1 / 14 » Optimization of critical paths in circuits with level-sensit... |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
TCAD
2008
13 years 5 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...
ISPD
2009
ACM
14 years 5 days ago
2009
ACM
Several approaches to post-silicon adaptation require feedback from a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit a...
DSN
2011
IEEE
12 years 5 months ago
2011
IEEE
—As process technology shrinks devices, circuits experience accelerated wearout. Monitoring wearout will be critical for improving the efficiency of error detection and correctio...