Sciweavers

Share
TCAD
2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm

9 years 2 months ago
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical to success. We present a new physical synthesis optimization for latch placement called RUMBLE (Rip Up and Move Boxes with Linear Evaluation) that uses a linear timing model to optimize timing by simultaneously re-placing multiple gates. RUMBLE runs incrementally and in conjunction with static timing analysis to improve the timing for critical paths that have already been optimized by placement, gate sizing, and buffering. Experimental results validate the effective
David A. Papa, Tao Luo, Michael D. Moffitt, Chin-N
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TCAD
Authors David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov
Comments (0)
books