100 search results - page 1 / 20 » Optimizing Address Assignment for Scheduling Embedded DSPs |
EUC
2004
Springer
13 years 10 months ago
2004
Springer
ICASSP
2008
IEEE
13 years 11 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
ICESS
2007
Springer
13 years 11 months ago
2007
Springer
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
ASPDAC
2001
ACM
13 years 8 months ago
2001
ACM
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...