19 search results - page 3 / 4 » Optimizing Logarithmic Arithmetic on FPGAs |
ARITH
1993
IEEE
13 years 9 months ago
1993
IEEE
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
ICASSP
2011
IEEE
12 years 9 months ago
2011
IEEE
Parameter trajectory generation for HMM-based speech synthesis is practically achieved using only fixed-point arithmetic with 32-bit integers. Since processors for embedded devic...
FCCM
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
FCCM
2006
IEEE
13 years 11 months ago
2006
IEEE
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...
ASAP
2008
IEEE
13 years 12 months ago
2008
IEEE
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...