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» Optimizing dominant time constant in RC circuits
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TCAD
1998
107views more  TCAD 1998»
9 years 11 months ago
Optimizing dominant time constant in RC circuits
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
Lieven Vandenberghe, Stephen P. Boyd, Abbas A. El ...
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
10 years 8 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...
RC
2006
46views more  RC 2006»
9 years 11 months ago
Towards Optimal Use of Multi-Precision Arithmetic: A Remark
If standard-precision computations do not lead to the desired accuracy, then it is reasonable to increase precision until we reach this accuracy. What is the optimal way of increa...
Vladik Kreinovich, Siegfried M. Rump
ISLPED
2004
ACM
118views Hardware» more  ISLPED 2004»
10 years 5 months ago
On optimality of adiabatic switching in MOS energy-recovery circuit
The principle of adiabatic switching in conventional energyrecovery adiabatic circuit is generally explained in literature with the help of the rudimentary RC circuit driven by a ...
Baohua Wang, Pinaki Mazumder
DAC
1995
ACM
10 years 3 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
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