50 search results - page 1 / 10 » Optimizing dominant time constant in RC circuits |
TCAD
1998
13 years 4 months ago
1998
— Conventional methods for optimal sizing of wires and transistors use linear resistor-capacitor (RC) circuit models and the Elmore delay as a measure of signal delay. If the RC ...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
RC
2006
13 years 4 months ago
2006
If standard-precision computations do not lead to the desired accuracy, then it is reasonable to increase precision until we reach this accuracy. What is the optimal way of increa...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
The principle of adiabatic switching in conventional energyrecovery adiabatic circuit is generally explained in literature with the help of the rudimentary RC circuit driven by a ...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...