22 search results - page 3 / 5 » Optimizing equivalence checking for behavioral synthesis |
TCAD
2008
13 years 5 months ago
2008
Abstract--Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and d...
AUTOMATICA
2006
13 years 5 months ago
2006
This paper revisits a well-known synthesis problem in iterative learning control, where the objective is to optimize a performance criterion over a class of causal iterations. The...
ICCTA
2007
IEEE
13 years 9 months ago
2007
IEEE
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
We present an algorithm that restructures the state transition graph STG of a sequential circuit so as to reduce power dissipation. The STG is modi ed without changing the behav...