2048 search results - page 2 / 410 » Optimizing pipelines for power and performance |
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
EMSOFT
2004
Springer
13 years 11 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
ESTIMEDIA
2009
Springer
13 years 3 months ago
2009
Springer
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
EURODAC
1995
IEEE
13 years 9 months ago
1995
IEEE
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
ISCAS
2007
IEEE
14 years 9 days ago
2007
IEEE
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...