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EURODAC
1995
IEEE

A hardware/software partitioning algorithm for pipelined instruction set processor

9 years 6 months ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to nd a set of HW implemented operations to achieve the highest performance of a pipelined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method is e ective and quite ecient.
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where EURODAC
Authors Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
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