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» Optimizing the Thermal Behavior of Subarrayed Data Caches
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ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 1 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
14 years 1 months ago
Parameterized transient thermal behavioral modeling for chip multiprocessors
In this paper, we propose a new architecture-level parameterized transient thermal behavioral modeling algorithm for emerging thermal related design and optimization problems for ...
Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Mur...
ASPDAC
2008
ACM
130views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Architecture-level thermal behavioral characterization for multi-core microprocessors
In this paper, we investigate a new architecture-level thermal characterization problem from behavioral modeling perspective to address the emerging thermal related analysis and o...
Duo Li, Sheldon X.-D. Tan, Murli Tirumala
DAC
2009
ACM
14 years 5 months ago
Thermal-aware data flow analysis
This paper suggests that the thermal state of a processor can be approximated using data flow analysis. The results of this analysis can be used to evaluate the efficacy of therma...
David Atienza, José Luis Ayala, Philip Bris...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
13 years 9 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...