32 search results - page 1 / 7 » Ordered escape routing based on Boolean satisfiability |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
Abstract-- Routing for high-speed boards is largely a timeconsuming manual task today. In this work we consider the ordered escape routing problem which is a key problem in boardle...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulat...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
We compare 12 new encodings for representing of FPGA detailed routing problems as equivalent Boolean Satisfiability (SAT) problems against the only 2 previously used encodings. We...
SIGSOFT
2005
ACM
14 years 5 months ago
2005
ACM
We present a context- and path-sensitive algorithm for detecting memory leaks in programs with explicit memory management. Our leak detection algorithm is based on an underlying e...
DATE
2008
IEEE
13 years 6 months ago
2008
IEEE
Many decision and optimization problems in Electronic Design Automation (EDA) can be solved with Boolean Satisfiability (SAT). Moreover, well-known extensions of SAT also find app...