5 search results - page 1 / 1 » Overlay aware interconnect and timing variation modeling for... |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
SLIP
2009
ACM
13 years 11 months ago
2009
ACM
Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interco...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
MONET
2006
13 years 4 months ago
2006
The radio frequency spectrum is a naturally limited resource of extraordinary value, as the key to the provision of important communication and information services. Traditionally,...