Sciweavers

230 search results - page 46 / 46
» PPM Reduction on Embedded Memories in System on Chip
Sort
View
CGO
2010
IEEE
14 years 10 days ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
BIRTHDAY
2009
Springer
14 years 7 days ago
Vertical Object Layout and Compression for Fixed Heaps
Research into embedded sensor networks has placed increased focus on the problem of developing reliable and flexible software for microcontroller-class devices. Languages such as ...
Ben Titzer, Jens Palsberg
FPL
2004
Springer
144views Hardware» more  FPL 2004»
13 years 9 months ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 9 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
DCC
2003
IEEE
14 years 5 months ago
Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding
Embedded computing systems are space and cost sensitive; memory is one of the most restricted resources, posing serious constraints on program size. Code compression, which is a s...
Yuan Xie, Wayne Wolf, Haris Lekatsas