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» Packet-Based Input Test Data Compression Techniques
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TVLSI
2010
13 years 3 days ago
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
Kanad Basu, Prabhat Mishra
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
13 years 9 months ago
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu ...
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
13 years 9 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
ICCD
2003
IEEE
145views Hardware» more  ICCD 2003»
14 years 2 months ago
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities
: Most of the recently discussed and commercially introduced test stimulus data compression techniques are based on low care bit densities found in typical scan test vectors. Data ...
Bernd Könemann
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
13 years 11 months ago
Functional constraints vs. test compression in scan-based delay testing
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
Ilia Polian, Hideo Fujiwara