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ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
12 years 10 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
CASES
2007
ACM
13 years 10 months ago
A fast and generic hybrid simulation approach using C virtual machine
Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to i...
Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Asch...
ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
13 years 10 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
IEEEPACT
2006
IEEE
14 years 8 days ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
FAST
2003
13 years 7 months ago
Using MEMS-Based Storage in Disk Arrays
Current disk arrays, the basic building blocks of highperformance storage systems, are built around two memory technologies: magnetic disk drives, and non-volatile DRAM caches. Di...
Mustafa Uysal, Arif Merchant, Guillermo A. Alvarez