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NOCS
2010
IEEE
13 years 3 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...
HPCA
2009
IEEE
14 years 6 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
HPCA
2006
IEEE
14 years 5 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev
CF
2009
ACM
13 years 12 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
CCECE
2006
IEEE
13 years 11 months ago
A Dynamic Associative E-Learning Model based on a Spreading Activation Network
Presenting information to an e-learning environment is a challenge, mostly, because ofthe hypertextlhypermedia nature and the richness ofthe context and information provides. This...
Phongchai Nilas, Nilamit Nilas, Somsak Mitatha