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» Parallel CABAC for low power video coding
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VLSISP
2008
147views more  VLSISP 2008»
13 years 3 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
ICASSP
2011
IEEE
12 years 8 months ago
A high throughput parallel AVC/H.264 context-based adaptive binary arithmetic decoder
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
Jia-Wei Liang, He-Yuan Lin, Gwo Giun Lee
PATMOS
2000
Springer
13 years 8 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
ICIP
2008
IEEE
14 years 6 months ago
Motion estimation with entropy coding considerations in H.264/AVC
In many modern video encoders, motion estimation is usually formulated as a Lagrangian cost function that balances motion prediction accuracy and the rate to transmit motion vecto...
Zhen Li, Alexis Michael Tourapis
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 5 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan