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» Parallel Hardware Architectures for the Cryptographic Tate P...
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DSD
2006
IEEE
135views Hardware» more  DSD 2006»
13 years 9 months ago
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
Jacques J. A. Fournier, Simon W. Moore
ISCA
2005
IEEE
88views Hardware» more  ISCA 2005»
13 years 11 months ago
Architecture for Protecting Critical Secrets in Microprocessors
We propose “secret-protected (SP)” architecture to enable secure and convenient protection of critical secrets for a given user in an on-line environment. Keys are examples of...
Ruby B. Lee, Peter C. S. Kwan, John Patrick McGreg...
ISVLSI
2002
IEEE
104views VLSI» more  ISVLSI 2002»
13 years 10 months ago
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montg...
Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, &Ccedi...
FCCM
2005
IEEE
132views VLSI» more  FCCM 2005»
13 years 11 months ago
Hardware Factorization Based on Elliptic Curve Method
The security of the most popular asymmetric cryptographic scheme RSA depends on the hardness of factoring large numbers. The best known method for factorization large integers is ...
Martin Simka, Jan Pelzl, Thorsten Kleinjung, Jens ...
CCS
1994
ACM
13 years 9 months ago
Protocol Failure in the Escrowed Encryption Standard
The Escrowed Encryption Standard (EES) defines a US Government family of cryptographic processors, popularly known as "Clipper" chips, intended to protect unclassified g...
Matt Blaze