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ICCAD
1990
IEEE
48views Hardware» more  ICCAD 1990»
13 years 9 months ago
Parallel Simulation Algorithms for Grid-Based Analog Signal Processors
Luis Miguel Silveira, Andrew Lumsdaine, Jacob Whit...
ICASSP
2008
IEEE
13 years 11 months ago
Mixed-signal parallel compressed sensing and reception for cognitive radio
A parallel structure to do spectrum sensing in Cognitive Radio (CR) at sub-Nyquist rate is proposed. The structure is based on Compressed Sensing (CS) that exploits the sparsity o...
Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler
ISCAS
2003
IEEE
105views Hardware» more  ISCAS 2003»
13 years 10 months ago
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
Roman Genov, Gert Cauwenberghs
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
13 years 10 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
IPPS
1996
IEEE
13 years 9 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson