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» Parallel VLSI Architectures for Cryptographic Systems
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GLVLSI
1997
IEEE
73views VLSI» more  GLVLSI 1997»
13 years 9 months ago
Parallel VLSI Architectures for Cryptographic Systems
Fabio Ancona, Alessandro De Gloria, Rodolfo Zunino
FCCM
2000
IEEE
148views VLSI» more  FCCM 2000»
13 years 9 months ago
An Adaptive Cryptographic Engine for IPSec Architectures
Architectures that implement the Internet Protocol Security (IPSec) standard have to meet the enormous computing demands of cryptographic algorithms. In addition, IPSec architectu...
Andreas Dandalis, Viktor K. Prasanna, José ...
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
13 years 10 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee
ISVLSI
2002
IEEE
104views VLSI» more  ISVLSI 2002»
13 years 10 months ago
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation
Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montg...
Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, &Ccedi...