8 search results - page 1 / 2 » Parallel and Fault-Tolerant Routing in Nanoscale Spin-Wave A... |
CDES
2007
13 years 6 months ago
2007
- In this paper, we present a number of parallel and fault-tolerant routing schemes for a set of nanoscale spin-wave architectures. The architectures considered here have several f...
PDPTA
2007
13 years 6 months ago
2007
- In this paper, we study the algorithm design aspects of three newly developed spin-wave architectures. The architectures are capable of simultaneously transmitting multiple signa...
CF
2006
ACM
13 years 11 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
NOCS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
Boundeddegreenetworks like deBruijn graphsor wrapped butterfly networks are very important from VLSI implementation point of view as well as for applications where the computing n...