22 search results - page 4 / 5 » Parallelization of loops with exits on pipelined architectur... |
ICIP
2003
IEEE
14 years 7 months ago
2003
IEEE
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
APCSAC
2000
IEEE
13 years 10 months ago
2000
IEEE
This paper briefly reviews the current research into RISC microprocessor architecture, which now seems to be so complex as to make the acronym somewhat of an oxymoron. In response...
CORR
2010
Springer
13 years 6 months ago
2010
Springer
The algorithms in the current sequential numerical linear algebra libraries (e.g. LAPACK) do not parallelize well on multicore architectures. A new family of algorithms, the tile a...
CHES
2009
Springer
14 years 6 months ago
2009
Springer
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
IPPS
2006
IEEE
14 years 5 days ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...