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    PATMOS
    2007
    Springer
    186views Modeling and Simulation» more  PATMOS 2007»
    Soft Error-Aware Power Optimization Using Gate Sizing
    13 years 11 months ago
    Soft Error-Aware Power Optimization Using Gate Sizing
    Download  www.cs.ucla.edu
    —Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
    Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
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    TCAD
    2008
    172views more  TCAD 2008»
    General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
    13 years 5 months ago
    General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
    Download  www.cs.ucla.edu
    Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
    Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
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    ICCD
    2008
    IEEE
    157views Hardware» more  ICCD 2008»
    Power-aware soft error hardening via selective voltage scaling
    14 years 2 months ago
    Power-aware soft error hardening via selective voltage scaling
    Download  www.ece.cmu.edu
    —Nanoscale integrated circuits are becoming increasingly sensitive to radiation-induced transient faults (soft errors) due to current technology scaling trends, such as shrinking...
    Kai-Chiang Wu, Diana Marculescu
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    DAC
    2008
    ACM
    142views Computer Architecture» more  DAC 2008»
    On the role of timing masking in reliable logic circuit design
    14 years 6 months ago
    On the role of timing masking in reliable logic circuit design
    Download  www.eecs.umich.edu
    Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
    Smita Krishnaswamy, Igor L. Markov, John P. Hayes
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    DSN
    2008
    IEEE
    180views Computer Networks» more  DSN 2008»
    An accurate flip-flop selection technique for reducing logic SER
    13 years 7 months ago
    An accurate flip-flop selection technique for reducing logic SER
    Download  www.ece.wisc.edu
    The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
    Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
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