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» Partitioning of VLSI Circuits and Systems
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ASPDAC
1999
ACM
113views Hardware» more  ASPDAC 1999»
13 years 9 months ago
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
C. K. Eem, J. W. Chong
DAC
1996
ACM
13 years 9 months ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
ASPDAC
1999
ACM
85views Hardware» more  ASPDAC 1999»
13 years 9 months ago
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits
Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, J...
ICCAD
1995
IEEE
96views Hardware» more  ICCAD 1995»
13 years 8 months ago
Delay optimal partitioning targeting low power VLSI circuits
Hirendu Vaishnav, Massoud Pedram