29 search results - page 5 / 6 » Path delay test compaction with process variation tolerance |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
ISLPED
2006
ACM
13 years 10 months ago
2006
ACM
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
SP
2002
IEEE
13 years 4 months ago
2002
IEEE
CX, a network-based computational exchange, is presented. The system's design integrates variations of ideas from other researchers, such as work stealing, non-blocking tasks...