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» Pattern generation for a deterministic BIST scheme
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ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 9 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
VTS
2002
IEEE
120views Hardware» more  VTS 2002»
13 years 10 months ago
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Madhu K. Iyer, Kwang-Ting Cheng
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
13 years 9 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
TCBB
2008
107views more  TCBB 2008»
13 years 5 months ago
Coclustering of Human Cancer Microarrays Using Minimum Sum-Squared Residue Coclustering
It is a consensus in microarray analysis that identifying potential local patterns, characterized by coherent groups of genes and conditions, may shed light on the discovery of pre...
Hyuk Cho, Inderjit S. Dhillon
EUROCAST
1997
Springer
156views Hardware» more  EUROCAST 1997»
13 years 9 months ago
A Computational Model for Visual Size, Location and Movement
The ability to detect object size, location and movement is essential for a visual system in either a biological or man made environment. In this paper we present a model for esti...
Miguel Alemán-Flores, K. Nicholas Leibovic,...