23 search results - page 3 / 5 » Pattern-based behavior synthesis for FPGA resource reduction |
CODES
2007
IEEE
14 years 4 days ago
2007
IEEE
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
TCAD
2011
13 years 7 days ago
2011
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
LCPC
2001
Springer
13 years 10 months ago
2001
Springer
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...