For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...
This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present A...
Harald P. E. Vranken, Friedrich Hapke, Soenke Rogg...
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Fo...