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TC
2010
13 years 3 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 3 days ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
IPSN
2003
Springer
13 years 10 months ago
A Robust Data Delivery Protocol for Large Scale Sensor Networks
Although data forwarding algorithms and protocols have been among the first set of issues explored in sensor networking, how to reliably deliver sensing data through a vast field...
Fan Ye, Gary Zhong, Songwu Lu, Lixia Zhang
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
12 years 9 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
ESAS
2007
Springer
13 years 11 months ago
Authenticating DSR Using a Novel Multisignature Scheme Based on Cubic LFSR Sequences
The problem of secure routing in mobile ad hoc networks is long-standing and has been extensively studied by researchers. Recently, techniques of aggregating signatures have been a...
Saikat Chakrabarti 0002, Santosh Chandrasekhar, Mu...