39 search results - page 1 / 8 » Performance Optimization By Wire and Buffer Sizing Under The... |
ICCD
2001
IEEE
14 years 2 months ago
2001
IEEE
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
ISQED
2002
IEEE
13 years 10 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
ASPDAC
1998
ACM
13 years 9 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
COMCOM
1999
13 years 4 months ago
1999
Asynchronous transfer mode (ATM) switches based on shared buffering are known to have better performance and buffer utilization than input or output queued switches. Shared buffer...