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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
13 years 11 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
SAMOS
2007
Springer
13 years 11 months ago
Evaluating Large System-on-Chip on Multi-FPGA Platform
This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on...
Ari Kulmala, Erno Salminen, Timo D. Hämä...
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
13 years 10 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
EMSOFT
2005
Springer
13 years 10 months ago
From multi-clocked synchronous processes to latency-insensitive modules
We consider the problem of synthesizing correct-by-construction globally asynchronous, locally synchronous (GALS) implementations from modular synchronous specifications. This in...
Jean-Pierre Talpin, Dumitru Potop-Butucaru, Julien...
SPAA
2006
ACM
13 years 11 months ago
A performance analysis of local synchronization
Synchronization is often necessary in parallel computing, but it can create delays whenever the receiving processor is idle, waiting for the information to arrive. This is especia...
Julia Lipman, Quentin F. Stout