121 search results - page 2 / 25 » Performance evaluation for system-on-chip architectures usin... |
DAC
2006
ACM
13 years 8 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
ISCA
2009
IEEE
14 years 20 days ago
2009
IEEE
Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framewo...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
VLDB
1991
ACM
13 years 9 months ago
1991
ACM
Multi-level transactions are a variant of open nested transactions in which the subtransactions correspond to operations at different levels of a layered system architecture. The ...
RTCSA
2007
IEEE
14 years 8 days ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...