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» Performance of Graceful Degradation for Cache Faults
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TC
2010
13 years 3 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
DSN
2011
IEEE
12 years 4 months ago
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan­ tages, such as better scalability, non-volatility and fast read access. However,...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,...
CASES
2006
ACM
13 years 11 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...
IPPS
2002
IEEE
13 years 9 months ago
Failure Behavior Analysis for Reliable Distributed Embedded Systems
Failure behavior analysis is a very important phase in developing large distributed embedded systems with weak safety requirements which do graceful degradation in case of failure...
Mario Trapp, Bernd Schürmann, Torsten Tettero...
ASC
2011
12 years 12 months ago
Autonomic fault-handling and refurbishment using throughput-driven assessment
A new paradigm for online EH regeneration using Genetic Algorithms (GAs) called Competitive Runtime Reconfiguration (CRR) is developed where performance is assessed based upon a b...
Ronald F. DeMara, Kening Zhang, Carthik A. Sharma