29 search results - page 6 / 6 » Performance of Output-Multibuffered Multistage Interconnecti... |
PARELEC
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper, we investigate the worst case performance of Earliest Due Date algorithm when applied to packet scheduling in distributed systems. We assume that the processing ele...
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
SIPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Low-Density Parity-Check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of the...
SIGCOMM
2004
ACM
13 years 11 months ago
2004
ACM
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...