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» Performance results for two of the NAS parallel benchmarks
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FDL
2007
IEEE
13 years 9 months ago
Transaction Level Modelling: A reflection on what TLM is and how TLMs may be classified
Transaction-level modelling (TLM) is a poorlyterm, promising a level of abstraction like RTL (register transfer level), where the key feature is a `transaction'. But unlike r...
Mark Burton, James Aldis, Robert Günzel, Wolf...
DSL
1997
13 years 7 months ago
Experience with a Language for Writing Coherence Protocols
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
Satish Chandra, James R. Larus, Michael Dahlin, Br...
JSW
2008
101views more  JSW 2008»
13 years 5 months ago
Graphical Mission Specification and Partitioning for Unmanned Underwater Vehicles
- The use of Unmanned Underwater Vehicles (UUVs) has been proposed for several different types of applications including hydrographic surveys (e.g., mapping the ocean floor and exp...
Gary Giger, Mahmut T. Kandemir, John Dzielski
TVCG
2008
147views more  TVCG 2008»
13 years 5 months ago
Cerebral: Visualizing Multiple Experimental Conditions on a Graph with Biological Context
Systems biologists use interaction graphs to model the behavior of biological systems at the molecular level. In an iterative process, such biologists observe the reactions of livi...
Aaron Barsky, Tamara Munzner, Jennifer L. Gardy, R...
DSN
2011
IEEE
12 years 5 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li