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ARCS
2008
Springer
13 years 7 months ago
A Novel Routing Architecture for Field-Programmable Gate-Arrays
Alexander Danilin, Martijn T. Bennebroek, Sergei S...
VLSISP
2008
108views more  VLSISP 2008»
13 years 5 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
13 years 11 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
13 years 10 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
FPGA
2001
ACM
162views FPGA» more  FPGA 2001»
13 years 10 months ago
Reprogrammable network packet processing on the field programmable port extender (FPX)
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extend...
John W. Lockwood, Naji Naufel, Jonathan S. Turner,...