36 search results - page 1 / 8 » Performances improvement of FPGA using novel multilevel hier... |
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
FPGA
2008
ACM
13 years 7 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
IPPS
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper investigates the design of parallel algorithmic strategies that address the efficient use of both, memory hierarchies within each processor and a multilevel clustered ...
GECCO
2010
Springer
13 years 7 months ago
2010
Springer
To successfully search multiple coadaptive subcomponents in a solution, we developed a novel cooperative evolutionary algorithm based on a new computational multilevel selection f...